Number of Positions: 1 Positions Filled: 0

Position Title: Sr. Staff Mask Design Engineer
Requisition #: 1586
Country: United States

State: California

City / Town: San Jose

Requisition Type: Contingent

Position Type: Full Time - Regular

Shift: 1st Shift (days)

Travel Required: 0 - 10%

Job Category: Engineering

Job Description:
Microsemi's SOC group:

The SOC Products Groups designs, develops, and markets low power, mixed signal and system critical FPGAs, offering the most comprehensive portfolio of system and power management solutions.

Summary:

As Mask Designer Senior Staff Engineer, you will be responsible for layout and verification of digital and mixed signal blocks including but not limited to ADCs, DACs, PLLs. You also will be responsible for functioning as a block/project lead as needed and the mentoring of other layout engineers in high speed analog techniques. The position reports to Mask Design Manager in Bethlehem, PA.

Responsibilities:

• Produce complex and non-routine design rule correct layouts of integrated circuit (IC) components from logic and/or schematics, diagrams or netlists.


• May oversee other designers in projects including: floor-planning, layout, and verification.


• Ensure that the quality of layout meets the first pass silicon success goal and achieves time to market objectives.


• Work with other layout and design engineers to resolve any technical issues that will affect layout to insure high quality.


• Establish and meet project objectives and milestones.


• Utilize CAD tools for verification to achieve the zero errors goal.


• As a project lead, provide direction to other personnel on a project and provide support to other project leads as needed.



• Teach and mentor other layout engineers in high speed analog and digital techniques
  Qualifications:
  Requirements:




• AAS/BS in EE, EET or CS or equivalent industry experience in electronics. 10+ years experience in CMOS high performance IC layout design.



• Experience with LINUX based CAD systems and MS Office tools required.


• Expert knowledge of Cadence full custom and standard cell layout design tools and various layout verification tools, such as Mentor Calibre.


• 3+ years experience in CMOS analog/mixed signal layout, including experience with some of the following types of circuits: CML circuits, RF components, including metal/metal capacitors, varactors, inductors, VCOs, High Speed I/O Buffers, Op-Amps, DACs/ADCs, cascoded current sources.


• Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching, bypass capacitor design and optimization, power supply buss construction using star connections, critical route shielding, triple well layout, ESD device and cell layout, and guard ring layout methods.


• Experience working in with deep submicron CMOS technology effects, such as stress mitigation (SA/SB/SC, well proximity), metal fill, and electromigration.


• Familiar with high frequency layout methods, including minimization of routing parasitics by iteratively using parasitic extraction tools such as Mentor's Calibre, minimization of routing parasitics by metal selection and matching of routing lines.


• A qualified candidate will be self-motivated, have the ability to work with minimal supervision, be comfortable taking direction, and able to coordinate and resolve issues with design engineering and technology development groups. In addition, candidates must be able to work within tight schedule constraints and maintain high quality standards with attention to detail


• Due to export compliance requirements, candidates must be US citizens