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          Apple ASIC Design Eng 4 in Santa Clara Valley California United States

          •Typically requires at least 10+ years of experience\n•Must be fluent in Verilog and SystemVerilog.\n•Must be very experienced with Synopsys VCS, NC-Verilog, or Modelsim.\n•Strong scripting abilities in PERL are needed, TCL or Python is a plus.\n•Good communications skills are required and prior customer support experience is a plus.\n•Must be conversant in VHDL.\n•Experience writing or maintaining the script or Makefile that builds the simulation program from RTL is a plus.\n•Familiarity with Debussy and/or DVE is considered a plus.\n•Knowledge of C and C++ is a plus.\n
          MS or BS Degree in technical discipline.
          As a member of our CAD team, you will develop, maintain, and enhance a system for regressing our designs. This system enables our design verification engineers to find bugs in our chips so that we can tape-out world-class silicon. Working alongside another engineer, the two of you will be responsible for development and support to our DV and design teams. You will have the opportunity to integrate your ideas and add new features to the system, as well as working with EDA vendors to manage their contributions.\n
          In this highly visible role, you will

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